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  LT1964 1 1964f n battery-powered instruments n low noise regulator for noise-sensitive instrumentation n negative complement to lt1761 family of positive ldos n low profile (1mm) thinsot tm package n low noise: 30 m v rms (10hz to 100khz) n low quiescent current: 30 m a n low dropout voltage: 340mv n output current: 200ma n fixed output voltage: C5v n adjustable output from C1.22v to C 20v n positive or negative shutdown logic n 3 m a quiescent current in shutdown n stable with 1 m f output capacitor n stable with aluminum, tantalum, or ceramic capacitors n thermal limiting 200ma, low noise, low dropout negative micropower regulator in thinsot the lt ? 1964 is a micropower low noise, low dropout negative regulator. the device is capable of supplying 200ma of output current with a dropout voltage of 340mv. low quiescent current (30 m a operating and 3 m a shut- down) makes the LT1964 an excellent choice for battery- powered applications. quiescent current is well controlled in dropout. other features of the LT1964 include low output noise. with the addition of an external 0.01 m f bypass capacitor, output noise is reduced to 30 m v rms over a 10hz to 100khz bandwidth. the LT1964 is capable of operating with small capacitors and is stable with output capacitors as low as 1 m f. small ceramic capacitors can be used without the necessary addition of esr as is common with other regulators. internal protection circuitry includes reverse output protection, current limiting, and thermal limiting. the device is available with a fixed output voltage of C5v and as an adjustable device with a C1.22v reference voltage. the LT1964 regulators are available in a low profile (1mm) thinsot package. , ltc and lt are registered trademarks of linear technology corporation. 1964 ta01a gnd shdn byp in out LT1964-5 1 f 10 f 0.01 f v in 5.4v to 20v 5v at 200ma 30 v rms noise C5v low noise regulator 10hz to 100khz output noise v out 100 v/div 1ms/div 1964 ta01b 30 v rms thinsot is a trademark of linear technology corporation. applicatio s u features typical applicatio u descriptio u
LT1964 2 1964f shdn pin voltage (with respect to gnd pin) ........................ C20v, 15v output short-circuit duration .......................... indefinite operating junction temperature range (note 10) ............................... C 40 c to 125 c storage temperature range ................. C 65 c to 150 c lead temperature (soldering, 10 sec).................. 300 c absolute axi u rati gs w ww u package/order i for atio uu w (note 1) order part number s5 part marking t jmax = 150 c, q ja ? 125 c/w to 250 c/w (note 13) see the applications information section ltvx LT1964es5-sd 5 out 4 adj gnd 1 top view s5 package 5-lead plastic sot-23 in 2 shdn 3 order part number s5 part marking t jmax = 150 c, q ja ? 125 c/w to 250 c/w (note 13) see the applications information section ltvz LT1964es5-5 order part number s5 part marking t jmax = 150 c, q ja ? 125 c/w to 250 c/w (note 13) see the applications information section ltvy LT1964es5-byp 5 out 4 adj gnd 1 top view s5 package 5-lead plastic sot-23 in 2 byp 3 5 out 4 shdn gnd 1 top view s5 package 5-lead plastic sot-23 in 2 byp 3 in pin voltage ........................................................ 20v out pin voltage (note 11) .................................... 20v out to in differential voltage (note 11) ....... C0.5v, 20v adj pin voltage (with respect to in pin) (note 11) ........... C0.5v, 20v byp pin voltage (with respect to in pin) ................................... 20v shdn pin voltage (with respect to in pin) (note 11) ........... C0.5v, 35v parameter conditions min typ max units regulated output voltage LT1964-5 v in = C5.5v, i load = C 1ma C4.925 C5 C5.075 v (notes 3, 9) C20v < v in < C6v, C200ma < i load < C1ma l C4.850 C5 C5.150 v adj pin voltage LT1964 v in = C2v, i load = C 1ma C1.202 C1.22 C1.238 v (notes 2, 3, 9) C20v < v in < C2.8v, C200ma < i load < C1ma l C1.184 C1.22 C1.256 v line regulation LT1964-5 d v in = C5.5v to C20v, i load = C 1ma l 15 50 mv LT1964 (note 2) d v in = C2.8v to C20v, i load = C 1ma l 112 mv load regulation LT1964-5 v in = C6v, d i load = C 1ma to C200ma 15 35 mv v in = C6v, d i load = C 1ma to C200ma l 50 mv LT1964 v in = C2.8v, d i load = C 1ma to C200ma 2 7 mv v in = C2.8v, d i load = C 1ma to C200ma l 15 mv electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. consult ltc marketing for parts specified with wider operating temperature ranges.
LT1964 3 1964f parameter conditions min typ max units dropout voltage i load = C 1ma 0.1 0.15 v v in = v out(nominal) i load = C 1ma l 0.19 v (notes 4, 5) i load = C 10ma 0.15 0.20 v i load = C 10ma l 0.25 v i load = C 100ma 0.26 0.33 v i load = C 100ma l 0.39 v i load = C 200ma 0.34 0.42 v i load = C 200ma l 0.49 v gnd pin current i load = 0ma l 30 70 m a v in = v out(nominal) i load = C 1ma l 85 180 m a (notes 4, 6) i load = C 10ma l 300 600 m a i load = C 100ma l 1.3 3 ma i load = C 200ma l 2.5 6 ma output voltage noise c out = 10 m f, c byp = 0.01 m f, i load = C200ma, bw = 10hz to 100khz 30 m v rms adj pin bias current (notes 2, 7) 30 100 na minimum input voltage (note 12) LT1964-byp l C1.9 C2.8 v i load = C200ma LT1964-sd l C1.6 C2.2 v shutdown threshold v out = off to on (positive) l 1.6 2.1 v v out = off to on (negative) l C1.9 C2.8 v v out = on to off (positive) l 0.25 0.8 v v out = on to off (negative) l C0.25 C0.8 v shdn pin current (note 8) v shdn = 0v C1 0.1 1 m a v shdn = 15v 6 15 m a v shdn = C15v C3 C9 m a quiescent current in shutdown v in = C6v, v shdn = 0v l 310 m a ripple rejection v in C v out = C1.5v(avg), v ripple = 0.5v p-p ,46 54db f ripple = 120hz, i load = C200ma current limit v in = C6v, v out = 0v 350 ma v in = v out(nominal) C1.5v, d v out = 0.1v l 220 ma input reverse leakage current v in = 20v, v out , v adj , v shdn = open circuit l 1ma electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: the LT1964 (adjustable version) is tested and specified for these conditions with the adj pin connected to the out pin. note 3: operating conditions are limited by maximum junction temperature. the regulated output voltage specification will not apply for all possible combinations of input voltage and output current. when operating at maximum input voltage, the output current range must be limited. when operating at maximum output current, the input voltage range must be limited. note 4: to satisfy requirements for minimum input voltage, the LT1964 (adjustable version) is tested and specified for these conditions with an external resistor divider (two 249k resistors) for an output voltage of C2.44v. the external resistor divider will add a 5 m a dc load on the output. note 5: dropout voltage is the minimum input to output voltage differential needed to maintain regulation at a specified output current. in dropout, the output voltage will be equal to: (v in + v dropout ). note 6: gnd pin current is tested with v in = v out(nominal) and a current source load. this means the device is tested while operating in its dropout region. this is the worst-case gnd pin current. the gnd pin current will decrease slightly at higher input voltages. note 7: adj pin bias current flows out of the adj pin. note 8: positive shdn pin current flows into the shdn pin. shdn pin current is included in the gnd pin current specification. note 9: for input-to-output differential voltages greater than 7v, a 50 m a load is needed to maintain regulation. note 10: the LT1964e is guaranteed to meet performance specifications from 0 c to 125 c. specifications over the C40 c to 125 c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. note 11: a parasitic diode exists internally on the LT1964 between the out, adj and shdn pins and the in pin. the out, adj and shdn pins cannot be pulled more than 0.5v more negative than the in pin during fault conditions, and must remain at a voltage more positive than the in pin during operation. note 12: for the LT1964-byp, this specification accounts for the operating threshold of the shdn pin, which is tied to the in pin internally. for the LT1964-sd, the shdn threshold must be met to ensure device operation. note 13: actual thermal resistance ( q ja ) junction to ambient will be a function of board layout. junction-to-case thermal resistance ( q jc ) measured at pin 2 is 60 c/w. see the thermal considerations section in the applications information.
LT1964 4 1964f typical perfor a ce characteristics uw output current (ma) 0 500 450 400 350 300 250 200 150 100 50 0 1964 g01 ?0 ?0 120 160 200 dropout voltage (mv) t j = 125 c t j = 25 c output current (ma) 0 500 450 400 350 300 250 200 150 100 50 0 1964 g02 ?0 ?0 120 160 200 dropout voltage (mv) t j 125 c = test point t j 25 c temperature ( c) 500 450 400 350 300 250 200 150 100 50 0 1964 g03 dropout voltage (mv) i l = 100ma i l = 50ma i l = 10ma i l = 1ma i l = 200ma 50 25 0 25 50 75 100 125 temperature ( c) ?0 ?5 ?0 ?5 ?0 ?5 ?0 ?5 ?0 ? 0 1964 g04 quiescent current ( a) v in = 6v r l = 250k ( for LT1964-5) i l = ? a (0 for LT1964-5) 50 25 0 25 50 75 100 125 v shdn = v in v shdn = 0v temperature ( c) 5.12 5.09 5.06 5.03 5.00 4.97 4.94 4.91 4.88 1964 g05 output voltage (v) i l = 1ma 50 25 0 25 50 75 100 125 temperature ( c) ?.240 ?.235 1.230 1.225 1.220 ?.215 1.210 1.205 1.200 1964 g06 adj pin voltage (v) i l = 1ma 50 25 0 25 50 75 100 125 input voltage (v) ?0 ?5 ?0 ?5 ?0 ?5 ?0 ? ? 1964 g07 quiescent current ( a) 0 ? ? ? ? ? ? ? ? ? ?0 t j = 25 c r l = v shdn = v in v shdn = 0v input voltage (v) ?0 ?5 ?0 ?5 ?0 ?5 ?0 ? ? 1964 g08 quiescent current ( a) 0 ? ? ? ? ? ? ? ? ? ?0 t j = 25 c r l = 250k i l = 5 a v shdn = v in v shdn = 0v input voltage (v) 3.0 2.5 2.0 1.5 1.0 0.5 0 1964 g09 gnd pin current (ma) 0 ? ? ? ? ? ? ? ? ? ?0 t j = 25 c v shdn = v in *for v out = 5v r l = 25 i l = 200ma* r l = 50 i l = 100ma* r l = 100 i l = 50ma* r l = 500 i l = 10ma* typical dropout voltage guaranteed dropout voltage dropout voltage quiescent current LT1964-5 output voltage LT1964-byp, LT1964-sd adj pin voltage LT1964-5 quiescent current LT1964-byp, LT1964-sd quiescent current LT1964-5 gnd pin current
LT1964 5 1964f typical perfor a ce characteristics uw 3.0 2.5 2.0 1.5 1.0 0.5 0 1964 g10 gnd pin current (ma) 0 ? ? ? ? ? ? ? ? ? ?0 r l = 12.2 i l = 100ma* r l = 24.4 i l = 50ma* r l = 122 i l = 10ma* t j = 25 c; v shdn = v in ; *for v out = ?.22v r l = 6.1 i l = 200ma* input voltage (v) 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 1964 g11 gnd pin current (ma) 0 ?0 ?0 ?20 ?60 ?00 v in = v out(nominal) ?1v t j = 50 c t j = 25 c t j = 125 c output current (ma) 2.5 2.0 1.5 1.0 0.5 0 0.5 1.0 1.5 2.0 2.5 1964 g12 shdn pin voltage (v) on on off temperature ( c) 50 25 0 25 50 75 100 125 10 8 6 4 2 0 ? ? ? ? ?0 1964 g13 shdn pin input current ( a) shdn pin voltage (v) ?0 ? ? ? ? 0 2 4 6 810 t j = 25 c positive current flows into the pin 12 9 6 3 0 ? ? ? 1964 g14 shdn pin input current ( a) temperature ( c) 50 25 0 25 50 75 100 125 v shdn = 15v v shdn = 15v v in = 15v positive current flows into the pin ?0 ?0 ?0 ?0 ?0 ?0 ?0 0 1964 g15 adj pin bias current (na) temperature ( c) 50 25 0 25 50 75 100 125 input/output differential (v) 0 600 500 400 300 200 100 0 1964 g16 ? ? ?2 ?6 ?0 current limit (ma) ? v out = 100mv temperature ( c) 600 500 400 300 200 100 0 1964 g17 current limit (ma) 50 25 0 25 50 75 100 125 v in = 7v v out = 0v 10 100 1k 10k 100k 1m frequency (hz) ripple rejection (db) 80 70 60 50 40 30 20 10 0 1964 g18 i l = 200ma v in = v out(nominal) ?1v + 50mv rms ripple c byp = 0 c out = 10 f c out = 1 f LT1964-byp, LT1964-sd gnd pin current gnd pin current vs i load shdn pin thresholds shdn pin input current shdn pin input current adj pin bias current current limit current limit input ripple rejection
LT1964 6 1964f temperature ( c) 60 58 56 54 52 50 48 46 44 1964 g19 ripple rejection (db) v in = v out(nominal) ?1v + 0.5v p-p ripple at f = 120hz i l = 200ma 50 25 0 25 50 75 100 125 temperature ( c) 3.0 2.5 2.0 1.5 1.0 0.5 0 1964 g20 minimum input voltage (v) note: the minimum input voltage accounts for the operating threshold of the shdn pin which is tied to the in pin internally i l = 200ma i l = 1ma 50 25 0 25 50 75 100 125 temperature ( c) 3.0 2.5 2.0 1.5 1.0 0.5 0 1964 g21 minimum input voltage (v) i l = 200ma i l = 1ma 50 25 0 25 50 75 100 125 note: the shdn pin threshold must be met to ensure device operation temperature ( c) 30 25 20 15 10 5 0 1964 g22 load regulation (mv) LT1964-5 LT1964-byp, LT1964-sd i l = 1ma to 200ma 50 25 0 25 50 75 100 125 frequency (hz) 0.1 output noise spectral density ( v/ hz) 1 10 1k 10k 100k 1964 g23 0.01 100 10 c out = 10 f i l = 200ma c byp = 1000pf c byp = 100pf c byp = 0 LT1964-5 LT1964-byp c byp = 0.01 f c byp (pf) 10 output noise ( v rms ) 140 120 100 80 60 40 20 0 100 1k 10k 1964 g24 c out = 10 f i l = ?00ma f = 10hz to 100khz LT1964-byp LT1964-5 140 120 100 80 60 40 20 0 load current (ma) output noise ( v rms ) 0.01 1964 g25 c out = 10 f c byp = 0.01 f LT1964-5 LT1964-byp LT1964-5 LT1964-byp, LT1964-sd c byp = 0 ? ?0 1k 0.1 100 typical perfor a ce characteristics uw input ripple rejection LT1964-byp minimum input voltage LT1964-sd minimum input voltage load regulation output noise spectral density rms output noise vs bypass capacitor rms output noise vs load current LT1964-5, 10hz to 100khz output noise, c byp = 0 LT1964-5, 10hz to 100khz output noise, c byp = 100pf v out (200 m v/div) c out = 10 m f 1ms/div 1964 g26.tif i load = C 200ma v out (100 m v/div) c out = 10 m f 1ms/div 1964 g27.tif i load = C 200ma
LT1964 7 1964f time ( s) 0 0.2 0.1 0 0.1 0.2 0 100 200 1964 g30 400 800 1200 1600 2000 load current (ma) output voltage deviation (v) v in = 6v c in = 10 f c out = 10 f time ( s) 0 0.04 0.02 0 0.02 0.04 0 100 200 1964 g31 40 80 120 160 20 60 100 140 180 200 load current (ma) output voltage deviation (v) v in = 6v c in = 10 f c out = 10 f typical perfor a ce characteristics uw LT1964-5, 10hz to 100khz output noise, c byp = 1000pf LT1964-5, 10hz to 100khz output noise, c byp = 0.01 m f v out (100 m v/div) c out = 10 m f 1ms/div 1964 g28.tif i load = C 200ma v out (100 m v/div) c out = 10 m f 1ms/div 1964 g29.tif i load = C 200ma LT1964-5, transient response, c byp = 0 LT1964-5, transient response, c byp = 0.01 m f pi fu ctio s uuu gnd (pin 1): ground. in (pin 2): power is supplied to the device through the input pin. a bypass capacitor is required on this pin if the device is more than six inches away from the main input filter capacitor. in general, the output impedance of a battery rises with frequency, so it is advisable to include a bypass capacitor in battery-powered circuits. a bypass capacitor in the range of 1 m f to 10 m f is sufficient. byp (pin 3, fixed/Cbyp devices): the byp pin is used to bypass the reference of the LT1964 to achieve low noise performance from the regulator. a small capacitor from the output to this pin will bypass the reference to lower the output voltage noise. a maximum value of 0.01 m f can be used for reducing output voltage noise to a typical 30 m v rms over a 10hz to 100khz bandwidth. if not used, this pin must be left unconnected. shdn (pin 3/4, Cshdn/fixed devices): the shdn pin is used to put the LT1964 into a low power shutdown state. the shdn pin is referenced to the gnd pin for regulator control, allowing the LT1964 to be driven by either positive or negative logic. the output of the LT1964 will be off when the shdn pin is pulled within 0.8v of gnd. pulling the shdn pin more than C1.9v or +1.6v will turn the LT1964 on. the shdn pin can be driven by 5v logic or open
LT1964 8 1964f the LT1964 is a 200ma negative low dropout regulator with micropower quiescent current and shutdown. the device is capable of supplying 200ma at a dropout voltage of 340mv. output voltage noise can be lowered to 30 m v rms over a 10hz to 100khz bandwidth with the addition of a 0.01 m f reference bypass capacitor. additionally, the refer- ence bypass capacitor will improve transient response of the regulator, lowering the settling time for transient load conditions. the low operating quiescent current (30 m a) drops to 3 m a in shutdown. in addition to the low quiescent current, the LT1964 incorporates several protection features which make it ideal for use in battery-powered systems. in dual supply applications where the regulator load is returned to a positive supply, the output can be pulled above ground by as much as 20v and still allow the device to start and operate. adjustable operation the adjustable version of the LT1964 has an output voltage range of C1.22v to C20v. the output voltage is set by the ratio of two external resistors as shown in figure 1. the device servos the output to maintain the voltage at the adj applicatio s i for atio wu u u pin at C1.22v referenced to ground. the current in r1 is then equal to C1.22v/r1 and the current in r2 is the current in r1 plus the adj pin bias current. the adj pin bias current, 30na at 25 c, flows through r2 out of the adj pin. the output voltage can be calculated using the formula in figure 1. the value of r1 should be less than 250k w to minimize errors in the output voltage caused by the adj pin bias current. note that in shutdown the output is turned off and the divider current will be zero. curves of adj pin voltage vs temperature and adj pin bias current vs temperature appear in the typical performance char- acteristics section. the adjustable device is tested and specified with the adj pin tied to the out pin and a 5 m a dc load (unless otherwise specified) for an output voltage of C1.22v. specifications for output voltages greater than C1.22v will be propor- tional to the ratio of the desired output voltage to C1.22v; (v out /C1.22v). for example, load regulation for an output current change of 1ma to 200ma is 2mv typical at v out = C1.22v. at v out = C12v, load regulation is: (C12v/C1.22v) ? (2mv) = 19.6mv pi fu ctio s uuu collector logic with a pull-up resistor. the pull-up resistor is required to supply the pull-up current of the open collector gate, normally several microamperes, and the shdn pin current, typically 3 m a out of the pin (for negative logic) or 6 m a into the pin (for positive logic). if unused, the shdn pin must be connected to v in . the device will be shut down if the shdn pin is open circuit. for the LT1964-byp, the shdn pin is internally connected to v in . a parasitic diode exists between the shdn pin and the input of the LT1964. the shdn pin cannot be pulled more negative than the input during normal operation, or more than 0.5v below the input during a fault condition. adj (pin 4, adjustable devices only): for the adjustable LT1964, this is the input to the error amplifier. the adj pin has a bias current of 30na that flows out of the pin. the adj pin voltage is C1.22v referenced to ground, and the output voltage range is C1.22v to C20v. a parasitic diode exists between the adj pin and the input of the LT1964. the adj pin cannot be pulled more negative than the input during normal operation, or more than 0.5v more negative than the input during a fault condition. out (pin 5): the output supplies power to the load. a minimum output capacitor of 1 m f is required to prevent oscillations. larger output capacitors will be required for applications with large transient loads to limit peak voltage transients. a parasitic diode exists between the output and the input. the output cannot be pulled more negative than the input during normal operation, or more than 0.5v below the input during a fault condition. see the applica- tions information section for more information on output capacitance and reverse output characteristics.
LT1964 9 1964f bypass capacitance and low noise performance the LT1964 may be used with the addition of a bypass capacitor from v out to the byp pin to lower output voltage noise. a good quality low leakage capacitor is recommended. this capacitor will bypass the reference of the LT1964, providing a low frequency noise pole. the noise pole provided by this bypass capacitor will lower the output voltage noise to as low as 30 m v rms with the addition of a 0.01 m f bypass capacitor. using a bypass capacitor has the added benefit of improving transient response. with no bypass capacitor and a 10 m f output capacitor, a C10ma to C200ma load step will settle to within 1% of its final value in less than 100 m s. with the addition of a 0.01 m f bypass capacitor, the output will stay within 1% for the same C10ma to C200ma load step (see LT1964-5 transient response in the typical characteris- tics section). however, regulator start-up time is inversely proportional to the size of the bypass capacitor. higher values of output voltage noise may be measured if care is not exercised with regard to circuit layout and testing. crosstalk from nearby traces can induce unwanted noise onto the output of the LT1964-x. applicatio s i for atio wu u u 1964 f01 gnd adj in out LT1964 v in v out + r1 r2 v out = 1.22v(1 + ) ?(i adj )(r2) v adj = 1.22v i adj = 30na at 25 c output range = 1.22v to 20v r2 r1 output capacitance and transient response the LT1964 is designed to be stable with a wide range of output capacitors. the esr of the output capacitor affects stability, most notably with small capacitors. a minimum output capacitor of 1 m f with an esr of 3 w or less is recommended to prevent oscillations. the LT1964 is a micropower device and output transient response will be a function of output capacitance. larger values of output capacitance decrease the peak deviations and provide improved transient response for larger load current changes. bypass capacitors, used to decouple individual components powered by the LT1964, will increase the effective output capacitor value. extra consideration must be given to the use of ceramic capacitors. ceramic capacitors are manufactured with a variety of dielectrics, each with different behavior across temperature and applied voltage. the most common di- electrics used are z5u, y5v, x5r, and x7r. the z5u and y5v dielectrics are good for providing high capacitances in a small package, but exhibit strong voltage and tem- perature coefficients as shown in figures 2 and 3. when used with a C5v regulator, a 10 m f y5v capacitor can exhibit an effective value as low as 1 m f to 2 m f over the operating temperature range. the x5r and x7r dielectrics result in more stable characteristics and are more suitable for use as the output capacitor. the x7r type has better stability across temperature, while the x5r is less expen- sive and is available in higher values. voltage and temperature coefficients are not the only sources of problems. some ceramic capacitors have a piezoelectric response. a piezoelectric device generates voltage across its terminals due to mechanical stress, similar to the way a piezoelectric accelerometer or micro- phone works. for a ceramic capacitor the stress can be induced by vibrations in the system or thermal transients. the resulting voltages produced can cause appreciable amounts of noise, especially when a ceramic capacitor is used for noise bypassing. a ceramic capacitor produced figure 4s trace in response to light tapping from a pencil. similar vibration induced behavior can masquerade as increased output voltage noise. figure 1. adjustable operation
LT1964 10 1964f figure 2. ceramic capacitor dc bias characteristics thermal considerations the power handling capability of the device will be limited by the maximum rated junction temperature (125 c). the power dissipated by the device will be made up of two components: 1. output current multiplied by the input/output voltage differential: i out ? (v in C v out ), and 2. ground pin current multiplied by the input voltage: i gnd ? v in . the gnd pin current can be found by examining the gnd pin current curves in the typical performance character- istics. power dissipation will be equal to the sum of the two components listed above. the LT1964 series regulators have internal thermal limit- ing designed to protect the device during overload condi- tions. for continuous normal conditions the maximum junction temperature rating of 125 c must not be exceeded. it is important to give careful consideration to all sources of thermal resistance from junction to ambient. additional heat sources mounted nearby must also be considered. for surface mount devices, heat sinking is accomplished by using the heat spreading capabilities of the pc board and its copper traces. copper board stiffeners and plated through-holes can also be used to spread the heat gener- ated by power devices. the following table lists thermal resistance for several different board sizes and copper areas. all measurements were taken in still air on 3/32" fr-4 board with one ounce copper. table 1. measured thermal resistance copper area thermal resistance topside* backside board area (junction-to-ambient) 2500mm 2 2500mm 2 2500mm 2 125 c/w 1000mm 2 2500mm 2 2500mm 2 125 c/w 225mm 2 2500mm 2 2500mm 2 130 c/w 100mm 2 2500mm 2 2500mm 2 135 c/w 50mm 2 2500mm 2 2500mm 2 150 c/w *device is mounted on topside. the thermal resistance junction-to-case (q jc ), measured at pin 2, is 60 c/w. dc bias voltage (v) change in value (%) 1964 f02 20 0 ?0 ?0 ?0 ?0 100 0 4 8 10 26 12 14 x5r y5v 16 both capacitors are 16v, 1210 case size, 10 f temperature ( c) ?0 40 20 0 ?0 ?0 ?0 ?0 100 25 75 1964 f03 ?5 0 50 100 125 y5v change in value (%) x5r both capacitors are 16v, 1210 case size, 10 f applicatio s i for atio wu u u figure 3. ceramic capacitor temperature characteristics figure 4. noise resulting from tapping on a ceramic capacitor LT1964-5 c out = 10 f c byp = 0.01 f i load = 200ma v out 1mv/div 100ms/div 1964 f04
LT1964 11 1964f calculating junction temperature example: given an output voltage of C5v, an input voltage range of C6v to C8v, an output current range of 0ma to C100ma, and a maximum ambient temperature of 50 c, what will the maximum junction temperature be? the power dissipated by the device will be equal to: i out(max) ? (v in(max) C v out ) + (i gnd ? v in(max) ) where, i out(max) = C100ma v in(max) = C8v i gnd at (i out = C100ma, v in = C8v) = C2ma so, p = C100ma ? (C8v + 5v) + (C2ma ? C8v) = 0.32w the thermal resistance (junction to ambient) will be in the range of 125 c/w to 150 c/w depending on the copper area. so the junction temperature rise above ambient will be approximately equal to: 0.32w ? 140 c/w = 44.2 c the maximum junction temperature will then be equal to the maximum junction temperature rise above ambient plus the maximum ambient temperature or: t jmax = 50 c + 44.2 c = 94.2 c protection features the LT1964 incorporates several protection features which make it ideal for use in battery-powered circuits. in addi- tion to the normal protection features associated with monolithic regulators, such as current limiting and ther- mal limiting, the device is protected against reverse input voltages and reverse output voltages. current limit protection and thermal overload protection are intended to protect the device against current overload conditions at the output of the device. for normal opera- tion, the junction temperature should not exceed 125 c. the output of the LT1964 can be pulled above ground without damaging the device. if the input is left open circuit or grounded, the output can be pulled above ground by 20v. for fixed voltage versions, the output will act like a large resistor, typically 500k w or higher, limiting current flow to less than 40 m a. for adjustable versions, the output will act like an open circuit, no current will flow into the pin. if the input is powered by a voltage source, the output will sink the short-circuit current of the device and will protect itself by thermal limiting. in this case, grounding the shdn pin will turn off the device and stop the output from sinking the short-circuit current. like many ic power regulators, the LT1964 series have safe operating area protection. the safe area protection activates at input-to-output differential voltages greater than C7v. the safe area protection decreases the current limit as the input-to-output differential voltage increases and keeps the power transistor inside a safe operating region for all values of forward input to-output voltage. the protection is designed to provide some output current at all values of input-to-output voltage up to the device breakdown. a 50 m a load is required at input-to-output differential voltages greater than C7v. when power is first turned on, as the input voltage rises, the output follows the input, allowing the regulator to start up into very heavy loads. during start-up, as the input voltage is rising, the input-to-output voltage differential is small, allowing the regulator to supply large output currents. with a high input voltage, a problem can occur wherein removal of an output short will not allow the output voltage to fully recover. other regulators, such as the lt1175, also exhibit this phenomenon, so it is not unique to the LT1964 series. the problem occurs with a heavy output load when the input voltage is high and the output voltage is low. common situations are immediately after the removal of a short-circuit or when the shdn pin is pulled high after the input voltage has already been turned on. the load line for such a load may intersect the output current curve at two points. if this happens, there are two stable operating points for the regulator. with this double intersection, the input supply may need to be cycled down to zero and brought up again to make the output recover. applicatio s i for atio wu u u information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
LT1964 12 1964f linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear.com ? linear technology corporation 2001 lt/tp 0502 2k ? printed in usa related parts package descriptio u part number description comments lt1120 125ma micropower low dropout regulator with includes 2.5v reference and comparator, v in = 3.5v to 36v, comparator and shutdown i q = 40 m a, n8 package lt1121 150ma micropower low dropout regulator v in = 4.2v to 30v, i q = 30 m a; thinsot, s8 and ms8 packages lt1129 700ma micropower low dropout regulator v in = 4.5v to 30v, i q = 50 m a; dd and s8 packages lt1175 800ma negative low dropout micropower regulator v in = 4.5v to 20v, i q = 45 m a, 0.26v dropout voltage, s8 and thinsot packages lt1611 inverting 1.4mhz switching regulator C5v at 150ma from 5v input, thinsot package lt1761 series 100ma, low noise, low dropout micropower regulators v in = 1.5v to 20v, i q =20 m a, 20 m v rms noise, thinsot package lt1762 series 150ma, low noise, ldo micropower regulators v in = 1.5v to 20v, i q =25 m a, 20 m v rms noise, ms8 package lt1763 series 500ma, low noise, ldo micropower regulators v in = 1.5v to 20v, i q =30 m a, 20 m v rms noise, s8 package lt1764a 3a, low noise, fast transient response ldo v in = 1.5v to 20v, 40 m v rms noise; dd and t5 packages lt1931/lt1931a inverting 1.2mhz/2.2mhz switching regulators C5v at 350ma from 5v input, thinsot package lt1962 300ma, low noise, ldo micropower regulator v in = 1.5v to 20v, i q =30 m a, 20 m v rms noise, ms8 package lt1963a 1.5a, low noise, fast transient response ldo v in = 1.5v to 20v, 40 m v rms noise; dd, t5, s8 and thinsot packages 1.50 ?1.75 (note 4) 2.80 bsc 0.30 ?0.45 typ 5 plcs (note 3) datum ? 0.09 ?0.20 (note 3) s5 tsot-23 0302 pin one 2.90 bsc (note 4) 0.95 bsc 1.90 bsc 0.80 ?0.90 1.00 max 0.01 ?0.10 0.20 bsc 0.30 ?0.50 ref note: 1. dimensions are in millimeters 2. drawing not to scale 3. dimensions are inclusive of plating 4. dimensions are exclusive of mold flash and metal burr 5. mold flash shall not exceed 0.254mm 6. jedec package reference is mo-193 3.85 max 0.62 max 0.95 ref recommended solder pad layout per ipc calculator 1.4 min 2.62 ref 1.22 ref s5 package 5-lead plastic tsot-23 (reference ltc dwg # 05-08-1635)


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